1. Field of the Invention
This invention relates in general to methods for providing electrical isolation between devices fabricated in the same semiconductor substrate and, more particularly, to improved methods for isolating adjacent devices in integrated circuits.
2. Background Art
It is commonplace in semiconductor device and integrated circuit technology to provide some means of controlling electrical coupling between devices in the same semiconductor substrate. Where the circuit design calls for the devices to have minimal coupling, a variety of means are used to provide electrical isolation, for example, dielectric isolation, junction isolation, and combinations thereof. The utility of a particular isolation scheme is a complex function of both the structural arrangement and the method of fabrication. These factors interact to affect the performance, ease of manufacture, reliability, manufacturing yield, and cost of production of the resulting devices.
Historically, junction isolation has been the most widely used technique for integrated circuits. With this approach, diffused regions extend from the surface of the semiconductor wafer through various active device layers to the underlying semiconductor substrate so as to form a P-N junction tub surrounding each of the isolated devices. Junction isolation suffers from a number of disadvantages which are well-known in the art.
More recently, it has become common to utilize dielectric regions rather than diffused regions as isolation walls. These dielectric regions or walls penetrate from the surface and separate the adjacent device regions. In order to obtain such dielectric isolation walls, a trench is etched in the semiconductor surface and then re-filled with a dielectric material, typically silicon dioxide. The dielectric filler is either grown in place from the semiconductor material itself, or deposited from an external source.
However, prior art dielectric isolation techniques and fabrication methods suffer from one or more disadvantages, such as for example, process complexity, high cost, incomplete isolation, lower manufacturing yield, poorer reliability, excessive die area consumption, and generation of excess material defects during manufacturing. Thus, a need continues to exist for isolation means and methods for semiconductor devices and integrated circuits which overcome or avoid one or more limitations of the prior art.
Accordingly, it is an object of the present invention to provide improved means and methods for electrical isolation of devices in a common semiconductor substrate, particularly for integrated circuits.
It is an additional object of the present invention to provide an improved manufacturing method for electrical isolation of adjacent devices which includes automatic self-alignment of buried layer regions, isolation regions, and channel-stop regions.
It is a further object of the present invention to provide an improved manufacturing method for electrical isolation of semiconductor devices which reduces defect generation during device manufacture.
It is an additional object of the present invention to provide an improved method for creating electrical isolation regions in semiconductor devices which incorporates an absorption sink for gettering heavy metals from critical device regions.
It is a further object of the present invention to provide an improved manufacturing method for fabricating electrically isolated semiconductor devices wherein the lateral separation between buried layer regions and channel-stop regions can be readily and conveniently controlled.
It is an additional object of the present invention to provide an improved manufacturing method for isolating semiconductor devices in a common substrate utilizing an isolation wall composed of a combination of superposed dielectric isolation and polycrystalline semiconductor regions.
It is a further object of the present invention to provide an improved manufacturing method for isolating semiconductor devices in a common substrate wherein the location and spacing of isolation walls, buried layer, and channel-stop regions is determined by a single masking layer.
As used herein, the words "polycrystalline" or "poly" are intended to include all non-single crystal forms of solids. As used herein, the words "dip etching" are intended to include all forms of blanket etching or erosion, and are not intended to be limited merely to wet chemical etching.